Marvell today introduced the industry's first 1.6T Ethernet PHY with 100G PAM4 electrical input/outputs (I/Os) in 5nm. The demand for increased bandwidth in the data center to support massive data growth is driving the transition to 1.6T (Terabits per second) in the Ethernet backbone. 100G serial I/Os play a critical role in the cloud infrastructure to help move data across compute, networking and storage in a power-efficient manner. The new Marvell® Alaska® C PHY is designed to accelerate the transition to 100G serial interconnects and doubles the bandwidth speeds of the previous generation of PHYs to bring scalability for performance-critical cloud workloads and applications such as artificial intelligence and machine learning.      

Marvell's 1.6T Ethernet PHY solution, the 88X93160, enables next-generation 100G serial-based 400G and 800G Ethernet links for high-density switches. The doubling of the signaling rate creates signal integrity challenges, driving the need for retimer devices for high port count switch designs. It's critical that retimer and gearboxes used for these applications are extremely power efficient. Implemented in the latest 5nm node, the Marvell 800GbE PHY provides a 40% savings in I/O power compared to existing 50G PAM4 based I/Os.  

"100G serial electrical signaling is vitally important because it serves as the foundational speed for the next generation of high-speed networks," said Alan Weckel, founder and technology analyst of 650 Group. "Challenges in signal integrity typically arise as I/O speeds increase. As the industry transitions to 100G serial electrical signaling on high density switches and optics, Marvell's 1.6T PHY is the only solution that's available in the market today to support this transition."

Marvell's 88X93160 is the industry's first PHY device fully compliant with IEEE's 802.3ck standards for 100G serial I/Os and the Ethernet Technology Consortium's 800GbE specifications. The device supports Gearboxing functionality which helps data center operators get the full bandwidth capabilities of the switch ASICs with 100G serial I/Os while interfacing with existing 50G PAM4 based 400G optical modules.

"Data center demand for 400GbE and beyond is experiencing exponential growth," said Achyut Shah, senior vice president and general manager of Marvell's PHY business unit. "We are very proud to offer the industry's first dual 1.6T PHY with 100G PAM4 I/Os designed for cloud data centers. Our 112G SerDes in 5nm boasts industry-leading power and greatly enhances the value that high-speed Ethernet brings to cloud data center applications."

With the introduction of the new PHY, Marvell is further extending its leadership in the high-speed Retimer and Gearbox segment with a broad portfolio spanning speeds from 10GbE to 800GbE and support for MACsec encryption and Class C compliant IEEE1588 PTP timestamping. With support for Ethernet speeds up to 800GbE, the new 88X93160 enables customers to build systems that comply with the latest IEEE and Ethernet Technology Consortium standards.

The Marvell 1.6T PHY incorporates the company's 112G 5nm SerDes solution that was announced in November of last year, offering breakthrough performance with the ability to operate at 112G PAM4 across channels with >40dB insertion loss. This 112G 5nm SerDes technology will be designed in Marvell's industry-proven Prestera® switch portfolio across data center, enterprise and carrier segments. It has also been adopted for use by multiple customers of Marvell's 5nm ASIC offering in high-performance infrastructure applications across a variety of markets.

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